Clock signals are used in virtually every IC and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the flip-flops in a circuit may change state. Clearly, the higher the frequency of the clock signal, the faster the circuit operates. Therefore, where performance is an issue, circuit designers usually prefer to use the fastest available clock that can be supported by the delays on the logic paths through the circuit. In other words, the performance of a circuit is typically limited by the logic delays on the slowest logic path. However, sometimes the longest path delay through the circuit is significantly shorter than the period of the available clock, and the frequency of the available clock becomes the limiting factor.
To overcome this limitation, circuit designers can double the frequency of a clock signal using a phase-lock loop (PLL) or delay-lock loop (DLL) circuit. However, PLL and DLL circuits consume a great deal of silicon area. Additionally, PLLs are often analog in nature and take an extremely long time to simulate, and a design that works in one manufacturing process may stop working when manufactured using another process. Therefore, PLLs are very difficult to design, and often are not feasible in a given circuit or system. DLLs are also very complicated and difficult to design. Therefore, clock doubling is often not feasible using known circuits and methods.
Therefore, it is desirable to provide a circuit and method that enables a circuit designer to double the frequency of an input clock without using a PLL or DLL, using a fairly simple circuit that consumes a relatively small amount of silicon area.